The present invention relates generally to serializer/deserializer (SERDES) devices. More particularly, the present invention relates to a transmitter having an elastic first-in first-out buffer in a fibre channel SERDES transmitter. This application is a continuation of U.S. patent application No. 10/621,297 filed on Jul. 17, 2003 (now U.S. Pat. No. 7,321,593). The disclosure of the above application is incorporated herein by reference in its entirety.
SERDES devices are commonly used where systems that internally handle multi-bit data words over parallel busses communicate with each other over a communications channel using serial bitstreams. Each SERDES device comprises a serializer that converts the data words to a serial bitstream before transmitting the bitstream over the channel, and a deserializer that converts a serial bitstream received from the channel to a plurality of data words.
One common application of SERDES devices is in storage area networks (SAN). FIG. 1 shows a SAN system 100 that comprises a SAN 102 connected to a local area network (LAN) 104 by a server 106. Computers and other network devices within LAN 104 can exchange data with storage devices within SAN 102 using server 106. A primary advantage of such a SAN system is that traffic between storage devices within SAN 102, such as to back up data from one storage device to another, does not burden LAN 104.
One common way to implement SAN 102 is according to the American National Standards Institute (ANSI) Fibre Channel standards, which define a high-performance data communications technology that supports very fast data rates (over 2 Gbps). FIG. 2 shows detail of a Fibre Channel implementation of SAN 102. SAN 102 comprises a plurality of SAN devices 206A through 206N that are connected to each other, and to server 106, by a fibre channel switch 204 over high-speed links such as multimode or single mode fiber optic cable.
FIG. 3 shows a SAN device 206 according to a conventional implementation. SAN device 206 comprises a host 302, such as a storage device, connected by a fibre channel interface that comprises a SERDES 304 to fibre channel switch 204.
SERDES 304 comprises a serialization unit 306 and a deserialization unit 308. Serialization unit 306 receives n-bit words of digital data over a parallel XMIT bus and a transmit clock XMIT_CLK from host 302, and transmits a serial bitstream of the digital data to fiber channel switch 204. Deserialization unit 308 receives a serial bitstream of digital data from fibre channel switch 204, and transmits n-bit words of the digital data over a parallel RECV bus to host 302.
Serialization unit 306 comprises a first-in first-out (FIFO) buffer 310, a serializer 312, a transmitter 314, and a phase-locked loop (PLL) 316. FIFO buffer 310 receives words of digital data from host 302 according to clock signal XMIT_CLK, and transmits the words of digital data to serializer 312, also according to clock signal XMIT_CLK. Serializer 312 converts the words of digital data to a serial bitstream. Transmitter 314 transmits the serial bitstream to fibre channel switch 204 according to a clock signal generated by PLL 316 according to clock signal XMIT_CLK.
Deserialization unit 308 comprises a receiver 318, a deserializer 320, and a FIFO buffer 322. Receiver 318 receives a serial bitstream of digital data from fibre channel switch 204. Deserializer 320 converts the serial bitstream to n-bit words of the digital data which are buffered by FIFO buffer 322 before transmission to host 302.
A significant disadvantage of SERDES 304 is that, while the rate of transmission of the serial bitstream by transmitter 314 is required by the Fibre Channel standards to have clock jitter less than 100 ppm, the clock signal XMIT_CLK that drives transmitter 314 can have significantly more jitter. While this clock accuracy is adequate for data rates up to 2 Gbps, it is insufficient to support higher data rates.